The present invention relates generally to a voltage conversion circuit, and more particularly to a charge pump type voltage conversion circuit which generates a boosted output voltage having reduced ripple voltage components.
Conventional voltage conversion circuits are disclosed, for example, in Japanese patent laid-open publication No. 8-212781, Japanese patent laid-open publication No. 6-165482, Japanese patent laid-open publication No. 63-018958, Japanese patent laid-open publication No. 63-018959, Japanese patent laid-open publication No. 5-276737, and the like.
The voltage conversion circuits described in these publications are used for obtaining a positive or negative output voltage which has a larger magnitude than that of a power supply voltage, from a single power supply voltage. Otherwise, the voltage conversion circuits described in these publications are used for obtaining an output voltage which has a smaller magnitude than that of a power supply voltage, from a single power supply voltage.
In order to compose such voltage conversion circuit on a printed circuit board, there is used a three terminal-type voltage regulator, a switching regulator which uses a coil component, or the like. However, the three terminal-type voltage regulator has a disadvantage that a power loss by a transistor of an output circuit stage thereof becomes large. Also, although a power loss of the switching regulator is relatively smaller than that of the three terminal-type voltage regulator, the switching regulator has a disadvantage that the size of the device becomes large because it uses a coil component.
In order to avoid the above-mentioned disadvantages, when, for example, a voltage conversion circuit is to be formed on an semiconductor integrated circuit device, a charge pump-type voltage conversion circuit is used. The charge pump-type voltage conversion circuit has the merits of low power loss, good compatibility with a semiconductor integrated circuit in a manufacturing process thereof, and the like.
As an example, a voltage conversion circuit outputting a positive voltage is used in a power supply circuit portion in an integrated circuit of an RS-232C (interface standard) driver/receiver, and the like. Also, a voltage conversion circuit outputting a negative voltage is used in a power supply circuit for a negative voltage source of an operational amplifier or a comparator, and the like.
Each of these voltage conversion circuits has a voltage conversion portion composed of a switched capacitor circuit which comprises switches and capacitors and which operates based on a clock signal supplied from a clock generator portion.
As another example, in Japanese patent laid-open publication No. 11-187545, there is disclosed a circuit structure which has a function of enabling or disabling a voltage raising operation, depending on whether or not a voltage corresponding to the difference between an output of a charge pump and a power supply voltage exceeds a reference voltage.
However, in such circuit structure, when a load is connected to an output terminal thereof, a relatively large voltage ripple arises at the output terminal due to the influence by the electric charges consumed by the load, and it is impossible to make an influence of such voltage ripple small.
With reference to the drawing, an explanation will be made on a practical example of a conventional voltage conversion circuit.
FIG. 5 is a circuit diagram illustrating an example of a conventional voltage conversion circuit. As shown in FIG. 5, the voltage conversion circuit includes a voltage detector circuit 1, a clock oscillator circuit 2a, a latch circuit 3, a charge pump circuit 4a, and a compensation capacitor CL. The voltage detector circuit 1 is a circuit which compares a divided output voltage VO2 of a boosted voltage output VO1 with a reference voltage VR1, and outputs a voltage detection signal xcfx861 depending on the result of the comparison. The clock oscillator circuit 2a performs a controlled oscillation operation in response to the voltage detection signal xcfx861, and outputs a clock signal xcfx862. The latch circuit 3 latches the clock signal xcfx862 outputted from the clock oscillator circuit 2 in response to the voltage detection signal xcfx861 from the voltage detector circuit 1. The charge pump circuit 4a charges capacitor elements C1 and C2 in response to the output signal of the latch circuit 3, and produces the boosted voltage output VO1. The compensation capacitor CL is coupled between the output terminal and the ground.
Also, the voltage detector circuit 1 comprises a comparator 11 for comparing the reference voltage VR1 and the divided voltage VO2 of the boosted voltage output VO1, and resistors R1 and R2 for producing the divided voltage VO2. These resistors R1 and R2 are serially coupled between the boosted voltage output VO1 and the ground, and the connection node between the resistor R1 and the resistor R2 is coupled with an inverting input (xe2x88x92side) of the comparator 11. A non-inverting input (+side) of the comparator 11 is coupled with the reference voltage VR1. When the divided voltage VO2 obtained by dividing the boosted voltage output VO1 is lower than the reference voltage VR1, the voltage detection signal xcfx861 which is an output of the comparator 11 becomes logically high. On the other hand, when the divided voltage VO2 is higher than the reference voltage VR1, the voltage detection signal xcfx861 becomes logically low.
The clock oscillator circuit 2a is basically composed of a ring oscillator comprising inverters I2-I4. An output of the inverter 14 of the final stage is fed back to an input of the inverter I2 of the first stage, via a transfer gate TG1 comprising an n-type MOS transistor and a p-type MOS transistor. Other inverters I5 and I6 designate output buffers for outputting the clock signal xcfx862. TG1 designates the transfer gate, Q1 designates a MOS switch, I1 designates an inverter for controlling the MOS switch Q1 and the transfer gate TG1. Since there exist parasitic capacitances C3-C5 at respective nodes in the ring oscillator having the above-mentioned structure, signal transition at each of the nodes becomes dull or blunted. Therefore, the clock oscillator circuit 2a requires buffering for wave shaping.
In the clock oscillator circuit 2a, the transfer gate TG1 is on-off controlled by the voltage detection signal xcfx861 generated depending on the potential level of the boosted voltage output VO1. The transfer gate TG1 becomes conductive only when the signal xcfx861 is logically high, and causes the ring oscillator circuit to oscillate and output the clock signal xcfx862 as an output thereof. On the other hand, when the voltage detection signal xcfx861 is logically low, an input node N1 of the inverter 12 is clamped to low by the inverter I1 and the transistor Q1, and fix the potential level of the clock signal xcfx862 to logically high. Generally, when an operation of a ring oscillator circuit is to be stopped, an input node is clamped to a low potential level or a high potential level, as in this circuit example, to avoid a floating condition of a potential level of each circuit node.
The latch circuit 3 has a transfer gate TG2 composed of an n-type MOS transistor and a p-type MOS transistor, an inverter 114, and clocked inverters 115 and 116. The transfer gate TG2 is controlled by the voltage detection signal xcfx861 from the voltage detector circuit 1. When the voltage detection signal xcfx861 is in a high potential level, that is, when the divided voltage VO2 produced from the boosted voltage output VO1 is lower than the reference voltage VR1, the transfer gate TG2 is turned on. When the voltage detection signal xcfx861 is in a low potential level, that is, when the divided voltage VO2 produced from the boosted voltage output VO1 is higher than the reference voltage VR1, the transfer gate TG2 is turned off. When the voltage detection signal xcfx861 becomes a low potential level, that is, when the transfer gate TG2 is turned off, the latch circuit 3 latches the clock signal xcfx862 of the clock oscillator circuit 2a just before turning off of the transfer gate TG2, by using the clocked inverters I15 and I16.
In the charge pump circuit 4a, the clock signal xcfx862 from the clock oscillator circuit 2a latched by the latch circuit 3 is converted into a pair of internal clock signals xcfx863 and xcfx864 which are complementary to each other, by inverters I7, I8 and I9. These internal clock signals xcfx863 and xcfx864 charge capacitance elements C1 and C2, respectively, and produce the boosted voltage output VO1. In the charge pump circuit 4a, the internal clock signals xcfx863 and xcfx864 have the phases which are inverted from each other, and the charge pump circuit 4a constitutes a complementary type circuit. MOS transistors Q2-Q5 constitute a circuit which functions as a buffer for delivering charged voltages of the capacitors C1 and C2 into the boosted voltage output VO1.
An explanation will now be made on an operation of the above-mentioned voltage conversion circuit. When a load circuit, for example, an operational amplifier, not shown in the drawing, is coupled to the line of the boosted output voltage VO1 and consumes an electric power, the boosted output voltage VO1 decreases, so that the divided voltage VO2 becomes lower than the reference voltage VR1. In such case, the voltage detection signal xcfx861 becomes logically high potential level, and the clock oscillator circuit 2a performs an oscillation operation and produces the clock signal xcfx862. When the clock signal xcfx862 is produced, the charge pump circuit 4a operates in a complementary manner and performs a voltage boost operation to produce the boosted output voltage VO1 which is supplied to the output terminal.
When the voltage VO1 at the output terminal raises and the divided voltage VO2 becomes higher than the reference voltage VR1, the voltage detection signal xcfx861 of the voltage detector circuit 1 becomes logically low, and the clock oscillator circuit 2a stops oscillation and, thereby, a voltage boosting operation of the charge pump circuit 4a is also stopped. As a result thereof, the rise of the boosted output voltage VO1 of the charge pump circuit 4a ceases. That is, the output voltage VO1 is maintained at a high potential level determined based on the reference voltage VR1, with a certain range of voltage variation centered around the high potential level (the width of this variation is called a ripple voltage).
Usually, it is desirable that the ripple voltage of the boosted output voltage VO1 is as small as possible. As one of the conventional methods of reducing the ripple voltage, when the divided voltage VO2 obtained by dividing the boosted output voltage VO1 becomes higher than the reference voltage VR1 and the voltage detection signal xcfx861 becomes low, operation of the charge pump circuit 4a is stopped as soon as possible. Also, when the divided voltage VO2 obtained by dividing the boosted output voltage VO1 becomes lower than the reference voltage VR1 due to the power consumption of the load circuit and the like and the voltage detection signal xcfx861 becomes high, operation of the charge pump circuit 4a is resumed as soon as possible. Thereby, the ripple voltage of the boosted output voltage VO1 is suppressed to a small value.
However, the above-mentioned conventional voltage conversion circuit has the following problems.
As the first problem, in the conventional voltage conversion circuit, the complementary type charge pump circuit is used and, therefore, two capacitors are required. Also, in order to suppress the ripple voltage, it is necessary to use elements each having large capacitance value. Therefore, number and volume of parts required in the charge pump circuit become large. Especially, the sizes of such capacitors are too large to incorporate into a semiconductor substrate, and usually such capacitors are provided as discrete parts disposed outside a semiconductor integrated circuit. Thus, when a voltage conversion circuit having a complementary type charge pump circuit is to be constituted, number of parts provided outside the semiconductor integrated circuit increases, and costs of the voltage conversion circuit also becomes large.
As the second problem, in case a non-complementary type charge pump circuit is used in place of the complementary type charge pump circuit, a magnitude of a ripple voltage becomes approximately twice as large as that of the complementary type charge pump circuit. The reason for this is as follows. When an operation of the clock oscillator circuit is to be halted, the clock signal just before halting the operation is latched. Therefore, when the next oscillation operation is restarted, the non-complementary type charge pump circuit does not always start operation from a voltage boosting operation.
As the third problem, since the potential level of the reference voltage is determined based on the power supply voltage, the potential level of the reference voltage may vary depending on variations of the potential level of the power supply voltage, and variations of the potential level of the reference voltage directly appear at the output terminal as variations of the boosted output voltage.
As the fourth problem, in the conventional voltage conversion circuit, it is always necessary to build the clock oscillator circuit into the semiconductor substrate and, therefore, the conventional voltage conversion circuit has disadvantages in a chip area, precision of a clock signal frequency, power consumption and the like. This is because, in the conventional voltage conversion circuit, when the potential level of the boosted output voltage reaches a predetermined potential level, an input or output node of the clock oscillator circuit is clamped to a low potential level or a high potential level to avoid a potential floating condition of each node of the clock oscillator circuit.
Therefore, it is an object of the present invention to obviate the disadvantages of the conventional voltage conversion circuit.
It is another object of the present invention to provide a voltage conversion circuit in which the number of parts can be decreased.
It is still another object of the present invention to provide a voltage conversion circuit in which the magnitude of a ripple voltage can be reduced.
It is still another object of the present invention to provide a voltage conversion circuit in which variations of a potential level of a reference voltage does not appear at an output terminal as variations of a boosted output voltage.
It is still another object of the present invention to provide a voltage conversion circuit in which it is possible to reduce ripple voltage components, even without building a clock oscillator circuit into a semiconductor substrate.
A voltage conversion circuit according to the present invention basically comprises: a detector means for detecting whether a boosted output voltage is larger or smaller than a predetermined reference voltage; a clock generating means for producing a second clock signal based on the result of detection by the detector means and on a first clock signal; a charge-pump type voltage conversion means which produces the boosted output voltage in response to the second clock signal; and a transfer means which allows or inhibits transfer of the second clock signal that is an output of the clock generating means to the voltage conversion means depending on the result of voltage detection by the detection means.
Also, in the present invention, when the condition of the transfer means is changed from the inhibited condition to the allowed condition based on the second clock signal outputted from the clock generating means, an operation of the voltage conversion means starts from a voltage boost sequence.
Further, in the present invention, it is not always necessary that the first clock signal is generated from the clock oscillator circuit on a semiconductor substrate, but it may be supplied from outside of the semiconductor substrate. Also, the second clock signal is obtained by dividing the first clock signal by using a divider circuit.
In an operation of such voltage conversion circuit, there is used a transfer circuit which is disposed between the clock generating circuit and the charge pump circuit and which is on-off controlled depending on the result of detection by the voltage detector circuit. Thereby, on and off of the operation of the charge pump circuit is controlled immediately in response to the result of voltage detection.
Especially, when the voltage detector circuit detects that the boosted output voltage is higher than a predetermined reference voltage, the transfer circuit is immediately turned off and prevents the second clock signal outputted from the clock generating circuit from being transferred to the charge pump circuit. Also, when the voltage detector circuit detects that the boosted output voltage is lower than the predetermined reference voltage, the transfer circuit is immediately turned on and transfers the second clock signal outputted from the clock generating circuit to the charge pump circuit.
The second clock signal transferred to the charge pump circuit is produced by dividing the first clock signal supplied from an oscillator circuit, which is arranged on a semiconductor substrate or outside of the semiconductor substrate, by using a divider circuit. In this case, when the voltage detector circuit detects that the boosted output voltage is higher than the predetermined reference voltage, the divider circuit becomes a reset condition. When the voltage detector circuit detects that the boosted output voltage is lower than the predetermined reference voltage, the divider circuit immediately starts a dividing operation of the first clock signal. Thereby, the timing of the second clock signal is controlled such that the charge pump circuit always starts operation from the voltage boost sequence.
Additionally, the reference voltage of the voltage detector circuit is determined based on an output of a reference voltage supply circuit which is less dependent on a power supply voltage and a temperature. Thereby, the variation of the output voltage caused by the variation of the reference voltage can be reduced.
According to an aspect of the present invention, there is provided a voltage conversion circuit comprising: a voltage detector means which detects whether a boosted output voltage of the voltage conversion circuit is larger or smaller than a predetermined reference voltage; a clock generating means which generates a clock signal based on the result of detection by the voltage detector means; a charge-pump type voltage conversion means which produces the boosted output voltage in response to the clock signal; and a transfer control means which allows or inhibits transfer of the clock signal to the voltage conversion means depending on the result of detection by the voltage detector means; wherein, when the condition of the transfer control means is changed from the inhibited condition to the allowed condition based on the clock signal outputted from the clock generating means, an operation of the voltage conversion means starts from a voltage boost sequence.
In this case, it is preferable that the transfer control means comprises a logic gate which receives the clock signal and a voltage detection signal showing the result of detection of the voltage detector means.
It is also preferable that the logic gate is an OR gate.
It is further preferable that the clock generating means comprises a divider circuit which divides an input clock signal supplied thereto and which is resettable based on the voltage detection signal from the voltage detector circuit.
According to another aspect of the present invention, there is provided a voltage conversion circuit comprising: a voltage detector circuit which detects whether a boosted output voltage of the voltage conversion circuit is larger or smaller than a predetermined reference voltage and which outputs a voltage detection signal depending on the result of detection; a clock oscillator circuit which has a divider circuit for dividing a first clock signal inputted thereto to generate a second clock signal and which has a reset circuit for resetting the divider circuit based on the voltage detection signal from the voltage detector circuit; a logic gate which perform logical operation of the second clock signal from the clock oscillator circuit and the voltage detection signal from the voltage detector circuit; and a charge-pump circuit which comprises a capacitor and switch circuit for charging the capacitor based on an output of the logic gate and which produces the boosted output voltage;
In this case, it is preferable that, when the boosted output voltage of the voltage conversion circuit becomes larger than the predetermined reference voltage, the charge pump circuit starts operation from a voltage boost sequence.
It is also preferable that the logic gate is an OR gate.
It is further preferable that the first clock signal is supplied by a clock supply circuit comprising an odd number of inverters coupled to form a ring oscillator and a buffer circuit coupled to the output of the ring oscillator.
It is advantageous that the divider circuit comprises a plurality of tandem coupled flip-flops which count the first clock signal to generate the second clock signal and which are resettable by the reset circuit.
It is also advantageous that the reset circuit resets the divider circuit based on an external reset signal or on the voltage detection signal from the voltage detector circuit.
It is further advantageous that the charge pump circuit is a non-complementary type charge pump circuit.
It is preferable that the voltage detector circuit comprises a comparator and a voltage divider circuit, the comparator receiving a divided voltage from the voltage divider circuit and a reference voltage supplied by a bandgap reference circuit.
It is also preferable that the voltage detector circuit comprises a comparator, an operational amplifier and a voltage divider circuit for dividing an output signal of the operational amplifier and supplying a divided voltage from the voltage divider circuit to an input of the comparator, the comparator and the operational amplifier receiving reference voltages each supplied by a bandgap reference circuit.
It is further preferable that the first clock signal is supplied to the clock oscillator circuit by a clock supply circuit disposed outside of a semiconductor integrated circuit including at least a portion of the voltage conversion circuit.
It is advantageous that the first clock signal is supplied to the clock oscillator circuit by a clock supply circuit integrated on a semiconductor substrate including at least a portion of the voltage conversion circuit.